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wireless components ask single conversion receiver 390mhz tda 5204 e1 version 1.0 specification december 2000 preliminary
edition 12.00 published by infineon technologies ag, balanstra?e 73, 81541 mnchen ? infineon technologies ag december 2000. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history current version: 1.0 as of 12.01.01 previous version: none page (in previous version) page (in current version) subjects (major changes since last revision)
product info product info wireless components specification, december 2000 package tda 5204 e1 preliminary product info general description the ic is a very low power consump- tion single chip ask single conver- sion receiver for receive frequencies between 385 and 406mhz. the receiver offers a high level of integra- tion and needs only a few external components. the device contains a low noise amplifier (lna), a double balanced mixer, a fully integrated vco, a pll synthesiser, a crystal oscillator, a limiter with rssi genera- tor, a data filter, a data comparator (slicer) and a peak detector. addition- ally there is a power down feature to save battery life. features low supply current (i s = 4.8ma typ.) supply voltage range 5v 10% temperature range -40 c...+85 c power down mode with very low supply current (50na typ) fully integrated vco and pll synthesiser rf input sensitivity < ? 110dbm 390mhz band selectable reference frequency limiter with rssi generation, operating at 10.7mhz 2nd order low pass data filter with external capacitors data slicer with self-adjusting threshold application keyless entry systems remote control systems fire alarm systems low bitrate communication systems ordering information type ordering code package tda 5204 q67037-a1169 p-tssop-28-1 available on tape and reel
1 table of contents 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 possible receive ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 3 2.5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -8 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.1 low noise amplifier (lna) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.2 mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.3 pll synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.5 limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.6 data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.7 data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.8 peak detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.9 bandgap reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 11
4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1 lna and automatic gain control (agc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 data filter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 quartz load capacitance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 quartz frequency calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 data slicer threshold generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 5 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 test board layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 5.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2 product description 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 possible receive ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 contents of this chapter
product description 2 - 2 tda 5204 e1 preliminary wireless components specification, december 2000 2.1 overview the ic is a very low power consumption single chip ask superheterodyne receiver (shr) for the frequency band 390mhz. the shr offers a high level of integration and needs only a few external components. the device contains a low noise amplifier (lna), a double balanced mixer, a fully integrated vco, a pll synthesiser, a crystal oscillator, a limiter with rssi generator, a data filter, a data comparator (slicer) and a peak detector. additionally there is a power down feature to save battery life. 2.2 application keyless entry systems remote control systems fire alarm systems low bitrate communication systems 2.3 features low supply current (is = 4.8ma typ.) supply voltage range 5v 10% power down mode with very low supply current (50na typ.) fully integrated vco and pll synthesiser rf input sensitivity < ? 110dbm frequency band 390mhz selectable reference frequency limiter with rssi generation, operating at 10.7mhz 2nd order low pass data filter with external capacitors data slicer with self-adjusting threshold temperature range -40 c...+85 c
product description 2 - 3 tda 5204 e1 preliminary wireless components specification, december 2000 2.4 possible receive ranges 385...406mhz (high-side injected) 406...428mhz (low-side injected) 781...823mhz (high-side injected) 803...844mhz (low-side injected) 2.5 package outlines p_tssop_28.eps figure 2-1 p-tssop-28-1 package outlines
3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 contents of this chapter
functional description 3 - 2 tda 5204 e1 preliminary wireless components specification, december 2000 3.1 pin configuration pin_configuration.wmf figure 3-1 ic pin configuration crst2 pwdn pdo data 3vout thres ffb opp sln slp limx lim csel lf TDA5204 1 2 3 4 5 6 7 8 9 10 11 12 13 14 crst1 vcc lni tagc agnd lno vcc mi mix agnd fsel ifo dgnd vdd 28 27 26 25 24 23 22 21 20 19 18 17 16 15
functional description 3 - 3 tda 5204 e1 preliminary wireless components specification, december 2000 3.2 pin definition and function table 3-1 pin definition and function pin no. symbol equivalent i/o-schematic function 1 crst1 external crystal connector 1 2 vcc 5v supply 3 lni lna input 4 tagc agc time constant control 5 agnd analogue ground return 6 lno lna output 7 vcc 5v supply 1 4.15v 3 1k 4 1k 4.3v 1.7v 4ua 1.5ua 1k 6
functional description 3 - 4 tda 5204 e1 preliminary wireless components specification, december 2000 8 9 mi mix mixer input complementary mixer input 10 agnd analogue ground return 11 fsel 390mhz: not applicable - has to be left open 12 ifo 10.7 mhz if mixer output 13 dgnd digital ground return 14 vdd 5v supply (pll counter cir- cuitry) 15 lf pll filter access point (loop filter) 8 2k 2k 9 1.7v 40k 11 1.2v 60 12 300ua 2.2v 4.5k 100 2.4v 30ua 30ua 4.8v 200 15
functional description 3 - 5 tda 5204 e1 preliminary wireless components specification, december 2000 16 csel 6.xx or 12.xx mhz quartz selector 17 18 lim limx limiter input complementary limiter input 19 slp data filter output data slicer positive input peak detector input 20 sln data slicer negative input 21 opp opamp noninverting input 80k 16 1.2v 330 2.4v 17 18 15k 15k 19 100 40u 10k 10k 20 10k 21 200
functional description 3 - 6 tda 5204 e1 preliminary wireless components specification, december 2000 22 ffb data filter feedback pin 23 thres agc threshold input 24 3vout 3v reference output 25 data data output 22 100k 23 10k 24 3v 25 200 80k
functional description 3 - 7 tda 5204 e1 preliminary wireless components specification, december 2000 26 pdo peak detector output 27 pdwn power down input vs --> power on gnd---> power down 28 crst2 external crystal connector 2 26 200 27 220k 220k 28 4.15v
functional description 3 - 8 tda 5204 e1 preliminary wireless components specification, december 2000 3.3 functional block diagram function_5204.wmf figure 3-2 main block diagram 3.4 functional blocks 3.4.1 low noise amplifier (lna) the lna is an on-chip cascode amplifier with a voltage gain of 15 to 20db. the gain figure is determined by the external matching networks situated ahead of lna and between the lna output lno (pin 6) and the mixer inputs mi and mix (pins 8 and 9). the noise figure of the lna is approximately 2db, the current consumption is 500a. the gain can be reduced by approximately 18db. the switching point of this agc action can be determined externally by applying a threshold voltage at the thres pin (pin 23). this voltage is compared internally with the received signal (rssi) level generated by the limiter circuitry. in case that the rssi level is higher than the threshold voltage the lna gain is reduced and vice versa. the threshold voltage can be generated by attaching a voltage divider between the 3vout pin (pin 24) which provides a temperature stable 3v output generated from the internal bandgap voltage and the thres pin as described in section 4.1. the time constant of the agc action can be deter- mined by connecting a capacitor to the tagc pin (pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operat- if filter vdd vcc lno mi mix ifo lim limx ffb opp slp sln data pdo slicer rssi thres lna rf tagc dgnd vcc agnd fsel csel pdwn crystal loop filter bandgap reference u ref tda 5204 agc reference 3vout 3 4 14 13 2/7 5/10 11 15 lf 16 1 28 27 24 23 26 25 20 19 21 22 18 17 12 9 8 6 crystal osc det : 128/64 vco : 1/2
functional description 3 - 9 tda 5204 e1 preliminary wireless components specification, december 2000 ing case and interference scenario to be expected during operation. the opti- mum choice of agc time constant and the threshold voltage is described in section 4.1. 3.4.2 mixer the double balanced mixer downconverts the input frequency (rf) 390mhz to the intermediate frequency (if) at 10.7mhz with a voltage gain of approximately 21db. a low pass filter with a corner frequency of 20mhz is built on chip in order to suppress rf signals to appear at the if output ( ifo pin). the if output is internally consisting of an emitter follower that has a source impedance of approximately 330 ? = to facilitate interfacing the pin directly to a standard 10.7mhz ceramic filter without additional matching circuitry. 3.4.3 pll synthesizer the phase locked loop synthesiser consists of a vco, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. the vco is including spiral inductors and varactor diodes. it ? s nominal centre frequency is 800mhz. the fsel pin (pin 11) has to be left open. no additional components are necessary. the oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. the vco signal is divided by two before it is fed to the mixer. the loop filter is also realised fully on-chip. 3.4.4 crystal oscillator the on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 6 and 12mhz range as the overall division ratio of the pll can be switched between 64 and 128 via the csel (pin 16 ) pin according to the following table. the calculation of the value of the necessary quartz load capacitance is shown in section 4.3, the quartz frequency calculation is expained in section 4.4. table 3-2 csel pin operating states csel crystal frequency open 6.xx mhz shorted to ground 12.xx mhz
functional description 3 - 10 tda 5204 e1 preliminary wireless components specification, december 2000 3.4.5 limiter the limiter is an ac coupled multistage amplifier with a cumulative gain of approximately 80db that has a bandpass-characteristic centred around 10.7mhz. it has an input impedance of 330 ? = to allow for easy interfacing to a 10.7mhz ceramic if filter. the limiter circuit acts as a receive signal strength indicator (rssi) generator which produces a dc voltage that is directly propor- tional to the input signal level as can be seen in figure 4.1. this signal is used to demodulate the ask receive signal in the subsequent baseband circuitry and to turn down the lna gain by approximately 18db in case the input signal strength is too strong as described in section 3.4.1 and section 4.1. 3.4.6 data filter the data filter comprises an op-amp with a bandwidth of 100khz used as a voltage follower and two 100k ? = on-chip resistors. along with two external capacitors a 2nd order sallen-key low pass filter is formed. the selection of the capacitor values is described in section 4.2. 3.4.7 data slicer the data slicer is a fast comparator with a bandwidth of 100 khz. this allows for a maximum receive data rate of approximately 120kbaud. the maximum achievable data rate also depends on the if filter bandwidth and the local oscil- lator tolerance values. both inputs are accessible. the output delivers a digital data signal (cmos-like levels) for the detector. the self-adjusting threshold on pin sln (pin 20) its generated by rc-term or peak detector depending on the baseband coding scheme. the data slicer threshold generation alternatives are described in more detail in section 4.5. 3.4.8 peak detector the peak detector generates a dc voltage which is proportional to the peak value of the receive data signal. an external rc network is necessary. the out- put can be used as an indicator for the signal strength and also as a reference for the data slicer. the maximum output current is approx. 900a.
functional description 3 - 11 tda 5204 e1 preliminary wireless components specification, december 2000 3.4.9 bandgap reference circuitry a bandgap reference circuit provides a temperature stable reference voltage for the device. a power down mode is available to switch off all subcircuits which is controlled by the pwdn pin (pin 27) as shown in the following table. the sup- ply current drawn in this case is typically 50na. table 3-3 pdwn pin operating states pdwn operating state open or tied to ground powerdown mode tied to vs receiver on
4 applications 4.1 lna and automatic gain control (agc) . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 data filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 quartz load capacitance calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 quartz frequency calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 data slicer threshold generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 contents of this chapter
applications 4 - 2 tda 5204 e1 preliminary wireless components specification, january 2001 4.1 lna and automatic gain control (agc) the agc extends the dynamic range of the receiver. the automatic gain control in the TDA5204 is a narrow-band control loop which compares the receive signal strength signal (rssi, 0.8v to 2.8v) from the lim- iter with a fixed threshold voltage applied to pin 23 (thres). in the following figure the internal circuitry of the lna automatic gain control is shown. lna_autom.wmf figure 4-1 lna automatic gain control circuitry the fixed voltage on pin 23 is generated on the external voltage divider. the comparator is a transimpedance amplifier (ota), which creates a positive cur- rent (+4.2ua) in the case the rssi level is larger than the threshold voltage. otherwise the current is -1.5ua. this leads to an asymmetric fast-attack and slow-release behaviour and thus to fast reaction to the low gain mode and slow reaction to the high gain mode. this current is converted into a control voltage over an external capacitor c attached to pin 4 (tagc) which defines the gain of the lna. the limits of the control voltages for the lna on pin4 are 1.67v for high gain mode and vcc-0.7v for low gain mode. pins: 24 23 4 lna r4 r5 u threshold rssi (0.8 - 2.8v) vcc gain control voltage ota +3v i load rssi > u threshold : i load =4.2a rssi < u threshold : i load = -1.5a u c c u c :< 2.6v : gain high u c :> 2.6v : gain low u cmax = v cc - 0.7v u cmin = 1.67v
applications 4 - 3 tda 5204 e1 preliminary wireless components specification, january 2001 rssi-agc.wmf figure 4-2 rssi level an permissive agc threhold level the value of the capacitor defines the response time of the agc. for a stable control loop the capacitor value should be at least 47nf. the agc can be disabled by tying the thres-pin either to gnd or to vcc as show here: lna high gain: - pin 23 (thres) shorted to vcc lna low gain: - pin 23 (thres) shorted to gnd in these cases capacitor and voltage divider are not necessary. lna always in high gain mode 0 0.5 1 1.5 2 2.5 3 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 input level at lna input [dbm] u thres voltage range rssi level range lna always in low gain mode rssi level
applications 4 - 4 tda 5204 e1 preliminary wireless components specification, january 2001 4.2 data filter design utilising the on-board voltage follower and the two 100k ? on-chip resistors a 2nd order sallen-key low pass data filter can be constructed by adding 2 exter- nal capacitors between pins 19 (slp) and 22 (ffb) and to pin 21 (opp) as depicted in the following figure and described in the following formulas 1 . filter_design.wmf figure 4-3 data filter design (1) (2) with (3) the quality factor of the poles where in case of a bessel filter a = 1.3617, b = 0.618 and thus q = 0.577 and in case of a butterworth filter a = 1.41, b = 1 and thus q = 0.71 example: butterworth filter with f 3db = 5khz and r = 100k ? : c 1 = 450pf, c 2 = 225pf 1. taken from tietze/schenk: halbleiterschaltungstechnik, springer berlin, 1999 pins: 22 21 19 rr 100k 100k c 1 c 2 c 1 2qb ? r2 f 3db ? ------------------------- = c2 b 4q r f 3db ?? ---------------------------------- = q b a ------ - =
applications 4 - 5 tda 5204 e1 preliminary wireless components specification, january 2001 4.3 quartz load capacitance calculation the value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in section 5.1.3 and by the quartz specifications given by the quartz manufacturer. quartz_load.wmf figure 4-4 determination of series capacitance value for the quartz oscillator the quartz oscillator input impedance consists of a negative resistance and an inductance l. crystal specified with load capacitance with c l the load capacitance (refer to the quartz crystal specification). examples with typ. values: 6.26 mhz: c l = 12 pf l=21uh c s = 8.6 pf 12.52 mhz: c l = 12 pf l=19uh c s = 5 pf these values may be obtained by putting two capacitors in series to the quartz. c s crystal input impedance z 1-28 TDA5204 pin 28 pin 1 () l f c c l s 2 2 1 1 + =
applications 4 - 6 tda 5204 e1 preliminary wireless components specification, january 2001 4.4 quartz frequency calculation the quartz frequency is calculated by using the following formula: ? qu = ( ? rf 10.7mhz) / r (1), with ? rf .... receive frequency +/- ... high-side / low-side injected ? lo .... local oscillator (pll) frequency ( ? rf 10.7) ? qu .... quartz oscillator frequency r .... ratio of local oscillator (pll) frequency and quartz frequency as shown in the subsequent table. example: f rf =390mhz f qu =(390mhz+10.7mhz) / 64 = 6.2609375mhz f qu =(390mhz+10.7mhz) / 32 = 12.521875mhz table 4-1 frequency range f rf high-side injected low-side injected fsel pin11 385...406mhz x open 406...428mhz x open 781...823mhz x gnd 803...844mhz x gnd table 4-3 fsel csel ratio r (f lo /f qu ) open open 64 open gnd 32 gnd open 128 gnd gnd 64 table 4-2 quartz crystal range csel pin16 6.xx mhz open 12.xx mhz gnd
applications 4 - 7 tda 5204 e1 preliminary wireless components specification, january 2001 4.5 data slicer threshold generation the threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. in case of a signal coding scheme without dc content such as manchester coding the threshold can be generated using an external r-c integrator as shown in the following . the cut-off frequency of the r-c integrator has to be lower than the lowest frequency appearing in the data signal. in order to keep distortion low, the minimum value for r is 20k ? . data_slice1.wmf figure 4-5 data slicer threshold generation with external r-c integrator another possibility for threshold generation is to use the peak detector in con- nection with two resistors and one capacitor as shown in the following figure. the component values are depending on the coding scheme and the protocol used. data_slice2.wmf figure 4-6 data slicer threshold generation utilising the peak detector pins: 20 19 r c 25 data out u threshold data slicer data filter pins: 20 19 25 data out u threshold data slicer data filter 26 peak detector c r r
5 reference 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 test board layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 contents of this chapter
reference 5 - 2 tda 5204 e1 preliminary wireless components specification, january 2001 5.1 electrical data 5.1.1 absolute maximum ratings warning the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. table 5-1 absolute maximum ratings, ambient temperature t amb =-40 c ... + 85 c # parameter symbol limit values unit remarks min max 1 supply voltage v s -0.3 5.5 v 2 junction temperature t j -40 +125 c 3 storage temperature t s -60 +150 c 4 thermal resistance r thja 114 k/w 5 esd integrity, all pins v esd -1 +1 kv hbm according to mil std 883d, method 3015.7
reference 5 - 3 tda 5204 e1 preliminary wireless components specification, january 2001 5.1.2 operating range within the operating range the ic operates as explained in the circuit descrip- tion. the ac/dc characteristic limits are not guaranteed. supply voltage: vcc = 4.5v .. 5.5v table 5-2 operating range, ambient temperature t amb = -40 c ... + 85 c # parameter symbol limit values unit test conditions l item min max 1 supply current i s 6.4 ma f rf = 390mhz 2 power down current i pwdn 250 na 3 receiver input level rf in -110 -13 dbm @ source impedance 50 ? , ber 2e-3, average power level, manchester encoded datarate 4kbit, 280khz if bandwidth, with agc 4 receive frequency f rf 385 406 mhz this value is guaranteed by design.
reference 5 - 4 tda 5204 e1 preliminary wireless components specification, january 2001 5.1.3 ac/dc characteristics ac/dc characteristics involve the spread of values guaranteed within the spec- ified voltage and ambient temp. range. typical characteristics are the median of the production. the device performance parameters marked with were measured on an infineon evaluation board as desdribed in section 5.2. cur- rents flowing into the device are denoted as positive currents and vice versa. table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v # parameter symbol limit values unit test conditions l item min typ max supply supply current 1 supply current, standby mode i s pdwn 50 150 na pin 27 (pdwn) open or tied to 0 v 2 supply current i s 4.8 5.5 ma lna signal input lni (pin 3), high gain mode 1 average power level at ber = 2e-3 (sensitivity) rf in -112 dbm manchester encoded datarate 4kbit, 280khz if bandwidth 2 input impedance, f rf = 390 mhz s 11 lna 0.879 / -31 deg 3 input level @ 1db c.p. f rf =390 mhz p1db lna -14 dbm 4 input 3 rd order intercept point f rf = 390 mhz iip3 lna -10 dbm f in = 390mhz 5 lo signal feedthrough at antenna port lo lni -119 dbm signal output lno (pin 6), high gain mode 1 gain f rf = 390 mhz s 21 lna 1.578 / 141.8deg 2 output impedance, f rf = 390 mhz s 22 lna 0.8822 / -12.13deg 3 voltage gain antenna to mi f rf = 390 mhz g antmi 21 db 4 noise figure nf lna 2 db excluding matching network loss - see appendix signal input lni, low gain mode 1 input impedance, f rf = 390 mhz s 11 lna 0.903 / -31.8deg 2 input level @ 1db c. p. f rf = 390 mhz p1db lna -7 dbm matched input
reference 5 - 5 tda 5204 e1 preliminary wireless components specification, january 2001 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) parameter symbol limit values unit test conditions l item min typ max signal input lni, v thres = gnd, low gain mode 3 input 3 rd order intercept point f rf = 390 mhz iip3 lna -13 dbm f in = 390mhz signal output lno, v thres = gnd, low gain mode 1 gain f rf = 390 mhz s 21 lna 0.1834 / 144deg 2 output impedance, f rf = 390 mhz s 22 lna 0.897 / -12.4deg 3 voltage gain antenna to mi f rf = 390 mhz g antmi 2 db signal 3vout (pin 24) 1 output voltage v 3vout 2.9 3 3.1 v 2 load current out i 3vout -50 a signal thres (pin 23) 1 input voltage range v thres 0 v s v see chapter 4.1 2 lna low gain mode v thres 0 0.5 v 3 lna high gain mode v thres 3.3 v s v 4 current in i thres_in -5 na signal tagc (pin 4) 1 current out, lna low gain state i tagc_out -2.5 -4.2 -5.5 a rssi > v thres 2 current in, lna high gain state i tagc_in 0.5 1.5 4a rssi < v thres mixer signal input mi/mix (pins 8/9) 1 input impedance, f rf = 390 mhz s 11 mix 0.9413 / -13.1deg 2 input 3 rd order intercept point iip3 mix -25 dbm signal output ifo (pin 12) 1 output impedance z ifo 330 ? 2 conversion voltage gain f rf =390 mhz g mix +21 db 3 noise figure, ssb ( ~ dsb nf+3db) nf mix 13 db 4 rf to if isolation a rf-if 46 db
reference 5 - 6 tda 5204 e1 preliminary wireless components specification, january 2001 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) parameter symbol limit values unit test conditions l item min typ max limiter signal input lim/x (pins 17/18) 1 input impedance z lim 264 330 396 ? 2 rssi dynamic range dr rssi 60 70 80 db 3 rssi linearity lin rssi 1 db 4 operating frequency (3db points) f lim 5 10.7 23 mhz 5 rssi level at data filter output slp rssi low 0.4 0.8 1.2 v limiter_in: 10uv 6 rssi level at data filter output slp rssi high 2.3 2.8 3.2 v limiter_in: 100mv data filter 1 max. useable bandwidth bw bb filt 100 khz slicer signal output data (pin 25) 1 max. useable bandwith bw bb slic 100 khz 2 low output voltage v slic_l 0 100 mv 3 high output voltage v slic_h vs-1.2 v s -1 vs-0.7 v 4 output current i slic_out -400 -800 -1100 a high level drive 5 output impedance rout 60 80 100 k ? low level drive peak detector signal output pdo (pin 26) 1 load current i load -500 -950 -1200 a 2 leakage current i leakage 0700 2000 na
reference 5 - 7 tda 5204 e1 preliminary wireless components specification, january 2001 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) parameter symbol limit values unit test conditions l item min typ max crystal oscillator signals crstl1, cristl 2, (pins 1/28) 1 operating frequency f crstl 1 14 mhz fundamental mode, series resonance 2 negative resistance @ ~ 6mhz re{z 1-28 } -750 ? 3 negatve resitance @ ~ 12mhz re{z 1-28 } -450 ? 4 input indutance @ ~ 6mhz im{z 1-28 }/ 2 f 21 uh 5 input inductance @ ~ 12mhz im{z 1-28 }/ 2 f 19 uh pll signal lf (pin 15) 1 tuning voltage relative to v s v tune 0.5 1.05 2v power down pin signal pdwn (pin 27) 1 powerdown mode on pwdn on 0 0.8 v 2 powerdown mode off pwdn off 2.8 v s v 3 input bias current i pwd 19 ua power on mode 4 start-up time until valid if signal is detected t su 1ms pll divider signal csel (pin 16) 1 f crstl range 6.xxmhz v csel 1.4 4v or open 2 f crstl range 12.xxmhz v csel 0 0.2 v 3 bias current csel i csel -5 a csel tied to gnd measured only in lab.
reference 5 - 8 tda 5204 e1 preliminary wireless components specification, january 2001 5.2 test circuit the device performance parameters marked with in section 5.1.3 were mea- sured on an infineon evaluation board. this evaluation board can be obtained together with evaluation boards of the accompanying transmitter device tda51xx in an evaluation kit that may be ordered on the infineon rke webpage www.infineon.com/rke test_circuit.wmf figure 5-1 schematic of the evaluation board i n f i n e o n t e c h n o l o g i e s d e s i g n c e n t e r g r a z t i t l e : t d a 5 2 0 0 / - 0 1 / - 0 2 e v a l u a t i o n b o a r d f i l e : - 1 0 v 2 . 0 d a t e : j u l . 1 9 , 1 9 9 9
reference 5 - 9 tda 5204 e1 preliminary wireless components specification, january 2001 5.3 test board layouts figure 5-2 top side of the evaluation board (tda5210 testboard is the same) figure 5-3 bottom side of the evaluation board
reference 5 - 10 tda 5204 e1 preliminary wireless components specification, january 2001 figure 5-4 component placement on the evaluation board
reference 5 - 11 tda 5204 e1 preliminary wireless components specification, january 2001 5.4 bill of materials the following components are necessary for evaluation of the TDA5204 at 390mhz without use of a microchip hcs515 decoder. table 5-4 bill of materials ref value specification r1 100k ? 0805, 5% r2 100k ? 0805, 5% r3 820k ? 0805, 5% r4 120k ? 0805, 5% r5 180k ? 0805, 5% r6 10k ? 0805, 5% l1 15nh toko, ptl2012-f15n0g l2 10pf a 0805,cog, 2% c1 1.8pf 0805, cog, 0.1pf c2 6.8pf 0805, cog, 0.1pf c3 6.8pf 0805, cog, 0.1pf c4 100pf 0805, cog, 5% c5 47nf 1206, x7r, 10% c6 12nh b toko, ptl2012-f15n0g c7 100pf 0805, cog, 5% c8 33pf 0805, cog, 5% c9 100pf 0805, cog, 5% c10 10nf 0805, x7r, 10% c11 10nf 0805, x7r, 10% c12 220pf 0805, cog, 5% c13 47nf 0805, x7r, 10% c14 470pf 0805, cog, 5% c15 47nf 0805, x7r, 10% c16 12pf 0805, cog, 0.1pf c17 12pf 0805, cog, 2% q2 (390mhz + 10.7mhz)/32 hc49/u, fundamental mode, c l = 12pf, 12.521875 mhz: jauch q12.521875-s11-1252-12-10/20 f1 sfe10.7ma5-a murata x2, x3 142-0701-801 johnson x1, x4, s1, s5 2-pole pin connector s4 3-pole pin connector, or not equipped ic1 tda 5204 infineon a. / b . the coil is at the place of the capacity and vice versa.
reference 5 - 12 tda 5204 e1 preliminary wireless components specification, january 2001 the following components are necessary in addition to the above mentioned ones for evaluation of the TDA5204 in conjunction with a microchip hcs515 decoder. table 5-5 bill of materials addendum ref value specification r21 22k ? 0805, 5% r22 100k ? 0805, 5% r23 22k ? 0805, 5% r24 820k ? 0805, 5% r25 560k ? 0805, 5% c21 100nf 1206, x7r, 10% c22 100nf 1206, x7r, 10% ic2 hcs515 microchip t1 bc 847b infineon d1 ls t670-jl infineon
list of figures list of figures - 1 tda 5204 e1 preliminary wireless components specification, december 2000 list of figures figure 2-1 p-tssop-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 figure 3-1 ic pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-2 main block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 figure 4-1 lna automatic gain control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-2 rssi level an permissive agc threhold level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 figure 4-3 data filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 figure 4-4 determination of series capacitance value for the quartz oscillator . . . . . . . . . . . . . . 4-5 figure 4-5 data slicer threshold generation with external r-c integrator . . . . . . . . . . . . . . . . . . 4-7 figure 4-6 data slicer threshold generation utilising the peak detector . . . . . . . . . . . . . . . . . . . 4-7 figure 5-1 schematic of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-2 top side of the evaluation board (tda5210 testboard is the same) . . . . . . . . . . . . . . 5-9 figure 5-3 bottom side of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 figure 5-4 component placement on the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
list of tables list of tables - 1 tda 5204 e1 preliminary wireless components specification, december 2000 list of tables table 3-1 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 table 3-3 pdwn pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 1 table 5-1 absolute maximum ratings, ambient temperature t amb =-40 c ... + 85 c . . . . . . . . . 5-2 table 5-2 operating range, ambient temperature t amb = -40 c ... + 85 c . . . . . . . . . . . . . . . . . 5-3 table 5-3 ac/dc characteristics with ta 25 c, vvcc = 4.5 ... 5.5 v . . . . . . . . . . . . . . . . . . . . . 5-4 table 5-4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-5 bill of materials addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

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